4.5 How to integrate your own design
To follow up this lesson, you need to complete Lesson 4.3 before. You also need to set up the PDK_ROOT and OPENLANE_ROOT to the correct location as specified during the previous lesson
To integrate your own design, you can use user_proj_example as a template, then modify it to match your design. In this part, we will use the seven_segment_seconds from Mattvenn as the module to be integrated.
First we can look at the verilog directory in caravel_user_project. It is the place where the verilog source files are kept.
verilog/ ├── dv │ ├── Makefile │ ├── README.md │ ├── cocotb │ │ ├── README.md │ │ ├── cocotb_tests.py │ │ ├── design_info.yaml │ │ ├── gpio_test │ │ │ ├── gpio_test.c │ │ │ └── gpio_test.py │ │ ├── hello_world │ │ │ ├── hello_world.c │ │ │ ├── hello_world.py │ │ │ └── hello_world.yaml │ │ ├── hello_world_uart │ │ │ ├── hello_world_uart.c │ │ │ ├── hello_world_uart.py │ │ │ └── hello_world_uart.yaml │ │ └── user_proj_tests │ │ ├── README.md │ │ ├── counter_la │ │ │ ├── counter_la.c │ │ │ ├── counter_la.py │ │ │ └── counter_la.yaml │ │ ├── counter_la_clk │ │ │ ├── counter_la_clk.c │ │ │ ├── counter_la_clk.py │ │ │ └── counter_la_clk.yaml │ │ ├── counter_la_reset │ │ │ ├── counter_la_reset.c │ │ │ ├── counter_la_reset.py │ │ │ └── counter_la_reset.yaml │ │ ├── counter_wb │ │ │ ├── counter_wb.c │ │ │ ├── counter_wb.py │ │ │ └── counter_wb.yaml │ │ ├── user_proj_tests.yaml │ │ └── user_proj_tests_gl.yaml │ ├── io_ports │ │ ├── Makefile │ │ ├── io_ports.c │ │ └── io_ports_tb.v │ ├── la_test1 │ │ ├── Makefile │ │ ├── la_test1.c │ │ └── la_test1_tb.v │ ├── la_test2 │ │ ├── Makefile │ │ ├── la_test2.c │ │ └── la_test2_tb.v │ ├── local-install.md │ ├── mprj_stimulus │ │ ├── Makefile │ │ ├── mprj_stimulus.c │ │ └── mprj_stimulus_tb.v │ ├── setup-cocotb.py │ └── wb_port │ ├── Makefile │ ├── wb_port.c │ └── wb_port_tb.v ├── gl │ ├── user_proj_example.nl.v │ ├── user_proj_example.v │ └── user_project_wrapper.v ├── includes │ ├── includes.gl+sdf.caravel_user_project │ ├── includes.gl.caravel_user_project │ └── includes.rtl.caravel_user_project └── rtl ├── defines.v ├── uprj_netlists.v ├── user_defines.v ├── user_proj_example.v └── user_project_wrapper.v
rtl folder contains the RTL verilog hardware description of our design.includes folder contains the definitions of the caravel user project. There are 3 options. One for RTL, one for gate-level (gl) simulation, and one for gate-level with delay simulation (gl+sdf).gl directory contains the gate-level netlist of the user_project_wrapper and the caravel test harness.dv directory contains the design verification codes including the testbench and the program to enable the io and start the design in the user project wrapper.To integrate a new design, the easiest way is to modify user_proj_example to initiate our design. By doing this, we can reuse the openlane configuration and avoid complicated implementation setup. We also need to create a testbench for our design in the dv folder.
Let’s start with the verilog hardware description of the design.
First we can download the new verilog file for seven_segment_seconds.v using the following commands:
curl https://raw.githubusercontent.com/mattvenn/seven_segment_seconds/mpw7/src/seven_segment_seconds.v -o verilog/rtl/seven_segment_seconds.v